The present invention generally relates to flash memory control.
When a flash memory controller issues a command, such as a data write (Program) command or an erase (Erase) command, to a flash memory, the flash memory executes an operation corresponding to a program command, an erase command, or another such command, and transitions to a Busy state during this time. Flash memory capacity has increased in recent years, and as such, the processing time corresponding to a command has become longer, and the time (Busy time) during which the flash memory is in the Busy state has grown to an extended period of time. In the case of a program and an erase in particular, the Busy state has transitioned to an order of milliseconds (ms).
When the flash memory is no longer in the Busy state, the flash memory controller issues a command, such as a different program command or a erase command, and executes the operation in the flash memory. The flash memory controller must therefore detect the fact that the flash memory is not in the Busy state.
As methods for detecting the Busy state of the flash memory, for example, there is (1) a method whereby the flash memory controller detects the fact that the flash memory is no longer in the Busy state on the basis of an FRDY signal outputted from an external pin (FRDY pin) of the flash memory; and (2) a method whereby the flash memory controller detects whether or not the flash memory is in the Busy state by executing status read (issuing a status command to the flash memory) and referencing a busy bit in status data sent (read) from the flash memory at intervals.
For example, in Japanese Patent Application Laid-open No. 2011-22778, there is disclosed a technique for confirming that either a flash memory program or erase has ended in order to detect the Busy state.